1. Field of the Invention
The present invention relates generally to copper interconnects. More particularly, the present invention relates to a method for making a dual damascene structure capable of suppressing hillocks in copper interconnects.
2. Description of the Prior Art
Damascene processes incorporated with copper interconnect technique are known in the art, which are also referred to as “copper damascene processes”. The copper damascene processes provide a solution to form a conductive wire coupled with an integral via plug without the need of etching copper. Either a single damascene or a dual damascene structure is used to connect devices and/or wires of an integrated circuit. Typically, at the end of a damascene process, a chemical mechanical polish (CMP) process is performed to planarize the surface of the semiconductor wafer so that the subsequent deposition and photolithographic processes will acquire an extended process window, and thus reliable multi-level interconnects can be formed.
FIG. 1 is a typical view of a semiconductor wafer 100 having aligned lower and upper damascened channels 102 and 104 with a connecting via 106. The lower and upper damascened channels 102 and 104 are respectively disposed in first and second channel dielectric layers 108 and 110. The via 106 is an integral part of the upper damascened channel 104 and is disposed in a via dielectric layer 112. A stop layer 122 is typically disposed between the via dielectric layer 112 and the second channel dielectric layer 110. The lower damascened channel 102 includes a barrier layer 126, which could optionally be a combined adhesion and barrier layer, and a seed layer 128 around a conductor core 130. The upper damascened channel 104 and the via 106 include a barrier layer 132, which could also optionally be a combined adhesion and barrier layer, and a seed layer 134 around a conductor core 136. The barrier layers 126 and 132 are used to prevent diffusion of copper into the adjacent areas of the semiconductor device.
In the single and dual damascene processes, after formation of the lower and upper damascened channels 102 and 104, respectively, the exposed conductor material 130 and 136 must be reduced and capped in-situ by the respective capping layers 120 and 124. With copper conductor materials, the capping layers 120 and 124 are formed by a process that first uses an ammonia or hydrogen plasma pre-treatment at 400° C. to reduce any residual copper oxide, which may be present on the exposed surfaces of the lower and upper damascened channels 102 and 104. This is followed by a silicon nitride deposition plasma enhanced chemical vapor deposition (PECVD) at 400° C. to provide the capping layers 120 and 124, which may be up to 500 angstroms in thickness.
However, the above-described prior art suffers from the formation of hillocks 140, or copper leakage lines, during the formation of capping layers 120 and 124 over exposed copper conductor materials. The hillocks 140, which can extend into both the capping layer and the dielectric layer, are capable of causing short circuits either immediately or over time. It has been found that the 400° C. ammonia plasma treatment causes the formation of small stress fractures in the lower and upper damascened channel dielectric layers 108 and 110, which allow the diffusion of copper to form hillocks 140. It has also been found that the PECVD deposition at 400° C. also develops stress fractures in the capping layers 120 and 124, which create hillocks 140, which extend through the capping layers 120 and 124.